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Figure 4 depicts the top-level architecture, in which each block of k bits represents a column of k/2 slices. The bypass (carryskip) action takes place when a carry is propagated by the least significant to the most significant bit position of a block, depending on the logic value of the signal’s Bpi (i = 1, … , m – 2). The latter are obtained by means of the circuit depicted in Figure 5. In order to assure that the signal’s Bpi is valid before the incoming carry arrives, the circuit is realized using the fast logic and routing resource available in CLBs.

The first is a macro-generatleast or most significant block of bits. com into only two adjacent columns of slice S1. The second implementation is obtained by assuming that just eight slices per column were available in the area in which the adder had to be placed. In this case, four columns of slice S1 were needed. Finally, a 64-bit adder consisting of four 16-bit blocks based on the logic we’ve proposed has been realized. The results and comparisons obtained in this case are also reported in Table 1.

You may download the layouts for our 16-bit carry-skip adder (on an AT40K) and 16-bit carry-select adder (generated by Atmel’s IDS) from the Circuit Cellar ftp site. Note that the skip circuit could have been one cell shorter, but we stretched it out to shorten some wiring. You can cIN Timing was performed for the AT40K40 at a speed level of –2. The worst-case readings were taken with the timing analyzer that comes with the Atmel IDS. There were a few contenders for the worst-case times. The first was the path from the least significant bit (either the operands or CIN; there isn’t much difference between the two) rippling through the least significant block, and then rippling through the middle block.