3D Integration for NoC-based SoC Architectures by Chuan Seng Tan (auth.), Abbas Sheibanyrad, Frédéric Pétrot,

By Chuan Seng Tan (auth.), Abbas Sheibanyrad, Frédéric Pétrot, Axel Jantsch (eds.)

Back conceal replica sequence: built-in Circuits and platforms 3D-Integration for NoC-based SoC Architectures by means of: (Editors) Abbas Sheibanyrad Frédéric Petrot Axel Janstch This e-book investigates at the delivers, demanding situations, and ideas for the 3D Integration (vertically stacking) of embedded structures attached through a community on a chip. It covers the full architectural layout method for 3D-SoCs. 3D-Integration applied sciences, 3D-Design options, and 3D-Architectures have emerged as subject matters severe for present R&D resulting in a vast variety of goods. This publication provides a entire, system-level evaluation of third-dimensional architectures and micro-architectures. •Presents a accomplished, system-level assessment of 3-dimensional architectures and micro-architectures; •Covers the total architectural layout strategy for 3D-SoCs; •Includes state of the art remedy of 3D-Integration applied sciences, 3D-Design innovations, and 3D-Architectures.

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Intuitively the reason for this is that the cost of transporting data across the chip to a central memory is much lower for a 3-D topology. Hence, if it is difficult to decentralize most memory accesses, the penalty will be lower for 3-D. However, the cost of centralized memory becomes steeper for more advanced technologies. 5 shows this effect for a 3D16 topology. 4 for 180€nm technology, it grows to a factor of 34 for a 17€nm technology. Hence, even if a 3-D topology can mitigate the cost of centralized memory, it is still growing exceedingly as technology advances due to the inverse effect on the performance of logic versus interconnect as a result of scaling.

S. Tan, Application of Self Assembly Monolayer (SAM) in Cu–Cu Bonding Enhancement at Low Temperature for 3-D Integration, Advanced Metallization Conference, Baltimore, October 13–15, 2009. C. E. Schulz (Eds), AMC 2009, pp. 259–266, ISBN 978-1-60511-218-3, Materials Research Society, 2010. 42. S. F. G. K. Goulet, and M. Bergkvist, Cu–Cu diffusion bonding enhancement at low temperature by surface passivation using self-assembled monolayer of alkane-thiol. Applied Physics Letters, 95(19), p. 192108, 2009.

24. A. Fan, A. Rahman, and R. Reif, Copper Wafer Bonding. Electrochemical and Solid-State Letters, 2(10), pp. 534–536, 1999. 26 C. S. Tan 25. R. Tadepalli, and Carl V. Thompson, Quantitative Characterization and Process Optimization of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits. Proc. of the IEEE 2003 International Interconnect Technology Conference, pp. 36–38, 2003. 26. S. N. Chen, A. Fan, and R. Reif, The Effect of Forming Gas Anneal on the Oxygen Content in Bonded Cu Layer.

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